1. Field of the Invention
This invention relates generally to digital phase lock loops, and more particularly to a wide band, wide operation range, general purpose digital phase locked loop (PLL) architecture.
2. Description of the Prior Art
Portable ultra large scaled integrated circuit (VLSI) systems require efficient power management schemes such as power supply voltage scaling, and clock frequency scaling on the fly to achieve optimal system/power performance. Phase locked loops, which generate the system clock, thus must be able to work under all these operating conditions and still maintain the loop stability. This implies that the PLL loop bandwidth has to be designed on the order of 10xc3x97 smaller than the smallest possible clock frequency. The scaling of power supply voltage on the fly further complicates the design by changing the semiconductor device parameters. The combined effect is that a designer usually must take a conservative approach and design a PLL which has a very low loop bandwidth (BW). On the other hand, the integration of a PLL and a large digital system generally has a large power supply and substrate noise injection associated with the digital circuitry, and thus, the large PLL output clock jitter. In order to reject those noises, a PLL is required to have a loop BW as large as possible. Such stability-performance trade offs create a great challenge on traditional analog PLL designs.
It is therefore advantageous and desirable to provide a completely digital PLL architecture capable of successfully addressing the foregoing stability-performance trade offs.
The present invention is directed to a wide band, wide operating range, general purpose digital phase locked loop (PLL) architecture. The entire PLL is running in the digital domain except for the Time Digitizer (T2D) and Digitally-Controlled-Oscillator (DCO). By calibrating the T2D and DCO on the fly, a constant PLL loop BW is achieved by using the calibrated Phase Frequency Detection (PFD) and DCO information to normalize the control loop correction regardless of the input clock frequency, power supply voltage, processing and temperature variations. PLL loop BW is completely decoupled from the operating conditions and semiconductor device variation. This means that the PLL loop BW can be chosen very aggressively to reject the noise, thus achieving a low jitter, high performance PLL. Furthermore, since this PLL can reliably operate over a wide operating range, it is a one-design-fits-all general purpose PLL.
According to one embodiment, a digital phase locked loop (PLL) comprises: a phase frequency detector configured to measure a difference (phase error) between a reference clock and a feedback clock and generate up and down pulses there from; a time digitizer configured to convert the phase error between the reference clock and the feedback clock into a phase error code in response to the up and down pulses; a digital controller configured to generate a digitally controlled oscillator (DCO) control code in response to the phase error code; and a DCO configured to generate an output clock in response to the DCO control code and further configured to generate the feedback clock, such that a substantially constant PLL bandwidth is achieved regardless of reference clock, power supply voltage, processing and temperature variations.
According to another embodiment, a digital phase locked loop (PLL) comprises: means for measuring a difference (phase error) between a reference clock and a feedback clock and generating up and down pulses there from; means for converting the phase error between the reference clock and the feedback clock into a phase error code in response to the up and down pulses; means for generating a digitally controlled oscillator (DCO) control code in response to the phase error code; and means for generating an output clock in response to the DCO control code and further configured to generate the feedback clock, such that a substantially constant PLL bandwidth is achieved regardless of reference clock, power supply voltage, processing and temperature variations.
According to yet another embodiment, a method of controlling a phase locked loop (PLL) bandwidth comprises the steps of: providing a digitally controlled PLL comprising: a phase frequency; a time digitizer; a digital controller; and a DCO; measuring a difference (phase error) between a reference clock and a feedback clock and generating up and down pulses there from via the phase frequency detector; converting the phase error between the reference clock and the feedback clock into a phase error code in response to the up and down pulses via the time digitizer; generating a digitally controlled oscillator (DCO) control code in response to the phase error code via the digital controller; and generating an output clock and the feedback clock in response to the DCO control code such that a substantially constant PLL bandwidth is achieved regardless of reference clock, power supply voltage, processing and temperature variations.